1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and more particularly, to a semiconductor integrated circuit provided with an ESD (electrostatic discharge) protection device for preventing breakdown of an internal circuit due to application of an ESD surge.
2. Description of Related Art
A semiconductor integrated circuit is generally provided with an ESD protection device for protecting an internal circuit from ESD surge applied to an input/output pad. The ESD protection device discharges the ESD surge applied to the input/output pad to a power supply line or a ground line, thereby protecting the internal circuit.
A thyristor is a typical ESD protection device. Since the thyristor has high discharge capacity and can reduce a parasitic capacitance, it is used as the ESD protection device for high-speed interface. The semiconductor integrated circuit including the thyristor as the ESD protection device is disclosed in “A PNP-Triggered SCR with Improved Trigger Techniques for High-Speed I/O ESD Protection in Deep Sub-Micron CMOS LSIs” by Y. Morishita (EOS/ESD Symposium 2005). This document discloses an ESD protection circuit which uses an NMOS transistor having a gate connected to a gate bias circuit, as a trigger device of the thyristor. In addition, U.S. Pat. No. 7,233,467 discloses protection of an input circuit connected to an input pad. In detail, U.S. Pat. No. 7,233,467 discloses circuit topology in which a resistance element is connected between a source of the NMOS transistor of an input buffer and the ground line. In the semiconductor integrated circuit in this publication, by passing a current to the resistance element through the thyristor when the ESD surge is applied, the voltage of the source of the NMOS transistor in the input buffer is increased, thereby protecting the NMOS transistor against the ESD surge.
FIG. 1 is a circuit diagram showing an example of configuration of a semiconductor integrated circuit 100 using the thyristor as the ESD protection device. The semiconductor integrated circuit 100 has a VDD pad 111 connected to a power supply line 101, an output pad 112 connected to an output signal line 102 and a VSS pad 113 connected to a ground line 103. A last stage output driver 116 of an internal circuit 115 is connected to the output pad 112. The last stage output driver 116 is formed of a PMOS transistor P1 and an NMOS transistor N1. The internal circuit 115 further has a previous stage pre-driver 117 for driving a gate of the NMOS transistor N1. The previous stage pre-driver 117 is formed of a PMOS transistor P2 and an NMOS transistor N2.
A thyristor 114 is connected between the output pad 112 and the VSS pad 113 to function as the ESD protection device. When the ESD surge is applied to the output pad 112, the thyristor 114 discharges the ESD surge to the ground line 103 to protect the last stage output driver 116. Although the semiconductor integrated circuit shown in FIG. 1 is not provided with a trigger device, in many cases, the trigger device is connected to the thyristor used as the ESD protection device and the thyristor is triggered by the trigger device.
A problem caused by using the thyristor as the ESD protection device is difficulty in properly triggering the thyristor, in particular, in triggering the thyristor with a low voltage. This problem is serious, especially, if a gate of the NMOS transistor N1 of the last stage output driver 116 is in the floating state when the ESD surge is applied to the output pad 112. When the NMOS transistor N2 of the previous stage pre-driver 117 is in the off state, the gate of the NMOS transistor N1 is set to the floating state and current flows through the NMOS transistor N1. When excessive current flows through the NMOS transistor N1 before the thyristor 114 operates, the NMOS transistor N1 is subjected to breakdown.
A method for solving such a problem is that a surge current flowing through a device to be protected (hereinafter referred to as a “protection target device”) is detected and the thyristor is operated in response to the detected surge current. By detecting the surge current flowing through the protection target device, and triggering and operating the thyristor according to the surge current before the protection target device is subjected to breakdown, the protection target device can be surely protected. Such a method is disclosed in “Current detection trigger scheme for SCR based ESD protection of Output drivers in CMOS technologies avoiding competitive triggering” by Benjamin Van Camp, et al. (EOS/ESD Symposium, 2005) and U.S. Patent Application Publication (2005/0286188).
FIG. 2 is a circuit diagram showing a configuration of a semiconductor integrated circuit configured to detect the current flowing through the protection target device and to trigger the thyristor. The semiconductor integrated circuit 200 has a thyristor 114, an output driver 116, a current detecting resistance element 118, diodes 119 and 120, an ESD clamp circuit 121, a power supply clamp circuit 122 and a diode 123. The semiconductor integrated circuit 200 shown in FIG. 2 is configured so that a current INMOS flowing through the NMOS transistor N1 of the output driver 116 is detected by the current detecting resistance element 118 and the thyristor 114 is triggered in response to the detected current INMOS.
A problem of the semiconductor integrated circuit in FIG. 2 is that since an N gate Gn of the thyristor 114 is electrically connected to the output pad 112, an output capacitance of the output pad 112 increases. A configuration of the thyristor 114 contributes to the increase in the output capacitance. FIG. 3 is a sectional view showing the configuration of the thyristor 114. An N well 132 and a P well 133 are formed in a P-type substrate 131 to be adjacent to each other. An N+ region 134 which function as the N gate Gn and a P+ region 135 connected to the output pad 112 are formed in the N well 132. Here, the “N+ region” refers to a region in which high-concentration n-type impurities are doped. The “P+ region” refers to a region in which high-concentration P-type impurities are doped. An N+ region 136 connected to the ground line 103 and the P+ region 137 which functions as a P gate Gp are formed in the P well 133. A P well 138 is formed in the P-type substrate 131, and a P+ region 139 connected to the ground line 103 is formed in the P well 138. In FIG. 3, a capacitance of the PN junction between the N well 132 and the P+ region 135 is shown as C1 and the capacitance of the PN junction between the N well 132 and the P well 133 is shown as C2.
As shown in FIGS. 4A and 4B, when the N gate Gn is connected to the output pad 112 (via the current detecting resistance element 118), an output capacitance Ctotal substantially corresponds to a capacitance C2. Since it is difficult to reduce a junction area between the N well 132 and the P well 133, it is difficult to make the capacitance C2 smaller, which means that it is difficult to reduce the output capacitance Ctotal. Increase in an output capacitance of the output pad 112 is disadvantageous in outputting an output signal at high speed.
Japanese Patent Application Publication (JP-P2005-340380A) discloses circuit topology configured to detect a current flowing through a protection target device and trigger the thyristor while reducing the parasitic capacitance (output capacitance). FIG. 5 is a circuit diagram showing a configuration of a semiconductor integrated circuit 300 disclosed in this publication. The semiconductor integrated circuit 300 has a thyristor 114, an output driver 116, diodes 119 and 120, a resistance element 124 and a PMOS transistor 125 used as a trigger device. The output driver 116 is formed from the PMOS transistor P1 and the NMOS transistor N1, and the resistance element 124 is connected between the NMOS transistor N1 and the ground line 103. A gate of the PMOS transistor 125 is connected to the power supply line 101, a drain thereof is connected to the P gate Gp of the thyristor 114 and a source thereof is connected to a connection node VO between the NMOS transistor N1 and the resistance element 124.
An operation of the semiconductor integrated circuit 300 in FIG. 5 is substantially as follows. When ESD surge is applied to the output pad 112, a parasitic bipolar transistor of the NMOS transistor N1 is turned on through a snap-back operation, so that a current flows into the connection node VO between the NMOS transistor N1 and the resistance element 124. Thereby, a voltage of the connection node VO rapidly increases. When the voltage of the connection node VO increases and a gate-source voltage Vgs of the PMOS transistor 125 (gate voltage using source voltage as reference) becomes lower than a threshold voltage—Vth, the PMOS transistor 125 is turned on to supply a trigger to the thyristor 114.
With the circuit configuration shown in FIG. 5, since both of the N gate Gn and the P gate GP of the thyristor 114 are electrically isolated from the output pad 112, an output capacitance of the output pad 112 can be reduced.
However, the semiconductor integrated circuit 300 in FIG. 5 has a problem that decrease in the resistance value of a path to which an output signal is outputted and reliability in triggering of the thyristor 114 cannot be achieved at a time. To allow the parasitic bipolar transistor of the NMOS transistor N1 to be turned on through the snap-back operation, a voltage of about 5V is generally required. It is difficult to make the gate voltage of the PMOS transistor 125 lower than a source voltage through the snap-back operation. In addition, in the semiconductor integrated circuit 300 in FIG. 5, to reduce a loss in outputting the output signal, the resistance value of the resistance element 124 must be made small. However, when the resistance value of the resistance element 124 is made small, increase in the voltage of the connection node VO becomes moderate. As a result, even when the ESD surge is applied, the thyristor 114 is hard to operate.
Such a problem is applied to the semiconductor integrated circuit 200 in FIGS. 4A and 4B. To reduce the loss in outputting the output signal, the resistance value of the current detecting resistance 118 must be made small. However, when the resistance value of the current detecting resistance element 118 is made small, difference in voltage between an anode and the N gate Gn of the thyristor 114 becomes smaller so that the thyristor 114 is hard to operate.